Mark Tehranipoor is currently the Sachio Semmoto Chair of the Department of Electrical and Computer Engineering (ECE) and the Intel Charles E. Young Preeminence Endowed Chair Professor in Cybersecurity at the the University of Florida. His current research projects include hardware security and trust, electronics supply chain security, IoT security, and reliable and testable VLSI design. He has published numerous journal articles and refereed conference papers and has given 230+ invited talks and keynote addresses. In addition, he has 22 patents issued, 28 pending invention disclosures, and has published 16 books of which two are textbooks. His projects have been sponsored by 50+ companies and Government agencies. He has also served as Program Chair of several IEEE/ACM sponsored conferences and workshops (HOST, ITC, DFT, D3T, DBT, NATW, etc.). He co-founded the IEEE International Symposium on Hardware-Oriented Security and Trust (HOST). He is a Fellow of IEEE, a Fellow of ACM, a Fellow of the National Academy of Inventors (NAI), a Golden Core Member of IEEE Computer Society, and a Member of ACM SIGDA.

Kimia Zamiri Azar is a research assistant professor in the Department of ECE at the University of Florida. She received a Ph.D. degree from the Department of ECE at George Mason University in 2021. Her research interests span hardware security and trust, supply chain security, System-on-Chips security validation and verification, and IoT security. She has one book, two book chapters, as well as 30+ publications in high-prestigious journals and conferences, including IEEE Transactions on Computers, IEEE Transactions on VLSI, IACR Transactions on Cryptographic Hardware and Embedded Systems (CHES), DAC, DATE, HOST, etc., with awards including nominations/recipient for Best Paper Award in IEEE Computer Society Annual Symposium on VLSI (ISVLSI) 2020, IEEE/ACM Conference on Computer-Aided-Design (ICCAD) 2020, IEEE HOST 2022, and DATE 2023.

Navid Asadizanjani is an associate professor in the department of electrical and computer engineering at university of Florida with an affiliation to the Materials Science and Engineering department. His research is mainly focused on. He investigates novel techniques for integrated circuits counterfeit detection/prevention, system and chip level reverse engineering, anti-reverse engineering, invasive and semi-invasive physical attacks, integrity analysis, etc.. Dr. Asadi is director of the Security and Assurance (SCAN) lab house to more than [...]M advanced imaging and characterization equipment. He also serves as the associate director of the Microelectronics Security Training (MEST) center and Florida Semiconductor Institute (FSI). He has received several best paper awards and is the co-founder of IEEE-PAINE conference.

Fahim Rahman is currently a Research Assistant Professor with the Electrical and Computer Engineering Department. His research has been sponsored by SRC, AFOSR, AFRL, DARPA, Cisco, TI, and NIST. His current research interests are in the domain of hardware and cybersecurity and trust, including electronic supply-chain security, CAD for security and automatic assessment, and hardware-assisted cybersecurity. He is a member of ACM.

Hadi Mardani Kamali is an assistant professor in the Department of ECE at the University of Central Florida. He received his Ph.D. degree from the Department of Electrical and Computer Engineering at George Mason University, 2021. His research delves into hardware security with a particular focus on exploiting IP protection techniques, design-for-trust for VLSI circuits, and CAD frameworks for security (design-for-security). His research contributions include the authorship of two books, three book chapters, three issued/pending patents, and numerous publications in top journals and conferences including IEEE Transactions on Computers, IEEE Transactions on VLSI, CHES, RAID, DAC, DATE, etc., with awards including nominations/recipients of Best Pape

Chapter 1 Quantifiable Assurance in Hardware.- Chapter 2 Advances in Logic Locking.- Chapter 3 Rethinking Hardware Watermark.- Chapter 4 SoC Security Verification using Fuzz, Penetration, and AI Testing.- Chapter 5 Runtime SoC Security Validation.- Chapter 6 Large Language Models for SoC Security.- Chapter 7 Power Side-channel Evaluation in Post-Quantum Cryptography.- Chapter 8 Digital Twin for Secure Semiconductor Lifecycle Management.- Chapter 9 Secure Physical Design.- Chapter 10 Secure Heterogeneous Integration.- Chapter 11 Materials for Hardware Security.