Dr. Steven H. Voldman is the first IEEE Fellow in the field of electrostatic discharge (ESD) for "Contributions in ESD protection in CMOS, Silicon On Insulator and Silicon Germanium Technology." Voldman was a member of the semiconductor development of IBM, Qimonda, and Intersil and worked as a full time consultant for Taiwan Semiconductor Manufacturing Corporation (TSMC) and a consultant on latchup, for the Samsung Electronics Corporation. He initiated the "ESD on Campus" program which was established to bring ESD lectures and interaction to university faculty and students internationally reaching over 40 universities in the United States, Korea, Singapore, Taiwan, Malaysia, Philippines, Thailand, India, China and Senegal. He is a recipient of 252 issued US patents and has written over 150 technical papers. He has served as an expert witness in patent litigation; and has also founded a limited liability corporation (LLC) consulting business supporting patents, patent writing and patent litigation. Steven Voldman provides tutorials and lectures on inventions, innovations, and patents.

Dr. Voldman is an author of the book series including ESD: Physics and Devices, ESD: Circuits and Devices, 2nd Edition of ESD: Circuits and Devices, ESD: Radio Frequency (RF) Technology and Circuits, Latchup, ESD: Failure Mechanisms and Models, ESD: Design and Synthesis, ESD Basics: From Semiconductor Manufacturing to Product Use, and Electrical Overstress (EOS): Devices, Circuits and Systems, ESD: Analog Circuits and Design,, as well as a contributor to the book Silicon Germanium: Technology, Modeling and Design andNanoelectronics: Nanowires, Molecular Electronics, and Nano-devices. In addition, the International Chinese editions of booksare also released.

About the Author xix

Preface xxi

Acknowledgments xxv

1 Electrostatic Discharge 1

1.1 Electricity and Electrostatic Discharge 1

1.1.1 Electricity and Electrostatics 1

1.1.2 Electrostatic Discharge 2

1.1.3 Key ESD Patents, Inventions, and Innovations 4

1.1.4 Table of ESD Defect Mechanisms 8

1.2 Fundamental Concepts of ESD Design 11

1.2.1 Concepts of ESD Design 12

1.2.2 Device Response to External Events 13

1.2.3 Alternate Current Loops 14

1.2.4 Switches 14

1.2.5 Decoupling of Current Paths 15

1.2.6 Decoupling of Feedback Loops 15

1.2.7 Decoupling of Power Rails 15

1.2.8 Local and Global Distribution 15

1.2.9 Usage of Parasitic Elements 16

1.2.10 Buffering 16

1.2.11 Ballasting 16

1.2.12 Unused Section of a Semiconductor Device, Circuit, or Chip Function 17

1.2.13 Impedance Matching between Floating and Nonfloating Networks 17

1.2.14 Unconnected Structures 17

1.2.15 Utilization of Dummy Structures and Dummy Circuits 17

1.2.16 Nonscalable Source Events 17

1.2.17 Area Efficiency 18

1.3 ESD, EOS, EMI, Electromagnetic Compatibility, and Latchup 18

1.3.1 Esd 18

1.3.2 Electrical Overstress 19

1.3.3 Electromagnetic Interference 19

1.3.4 Electromagnetic Compatibility 19

1.3.5 Latchup 19

1.4 ESD Models 19

1.4.1 Human Body Model 20

1.4.2 Machine Model 21

1.4.3 Cassette Model (Small Charge Model) 24

1.4.4 Charged Device Model 24

1.4.5 Transmission Line Pulse 25

1.4.6 Very Fast Transmission Line Pulse 26

1.5 ESD and System-Level Test Models 28

1.5.1 IEC 61000-4-2 29

1.5.2 Human Metal Model 29

1.5.3 IEC 61000-4-5 30

1.5.4 Charged Board Model 31

1.5.5 Cable Discharge Event 32

1.5.5.1 CDE and Scaling 36

1.5.5.2 CDE-Cable Measurement Equipment 37

1.5.5.3 Cable Configuration-Test Configuration 38

1.5.5.4 Cable Configuration-Floating Cable 38

1.5.5.5 Cable Configuration-Held Cable 38

1.5.5.6 CDE-Peak Current versus Charged Voltage 39

1.5.5.7 CDE-Plateau Current versus Charged Voltage 39

1.6 Time Constants 39

1.6.1 Characteristic Times 39

1.6.2 Electrostatic and Magnetostatic Time Constants 39

1.6.2.1 Charge Relaxation Time 39

1.6.2.2 Magnetic Diffusion Time 40

1.6.2.3 Electromagnetic Wave Transit Time 40

1.6.3 Thermal Time Constants 42

1.6.3.1 Heat Capacity 42

1.6.3.2 Thermal Diffusion 42

1.6.3.3 Heat Transport Equation 42

1.6.4 Thermal Physics Time Constants 43

1.6.4.1 Adiabatic, Thermal Diffusion Timescale, and Steady State 44

1.6.5 Semiconductor Device Time Constants 45

1.6.5.1 Depletion Region Transit Time 45

1.6.5.2 Silicon Diode Storage Delay Time 45

1.6.5.3 Bipolar Base Transit Time 46

1.6.5.4 Bipolar Turn-on Transient Time 46

1.6.5.5 Bipolar Turn-off Transient Time 46

1.6.5.6 Bipolar Emitter Transition Capacitance Charging Time 46

1.6.5.7 Bipolar Collector Capacitance Charging Time 47

1.6.5.8 SCR Time Response 47

1.6.5.9 MOSFET Transit Time 47

1.6.5.10 MOSFET Drain Charging Time 48

1.6.5.11 MOSFET Gate Charging Time 48

1.6.5.12 MOSFET Parasitic Bipolar Response Time 48

1.6.6 Circuit Time Constants 49

1.6.6.1 Pad Capacitance 49

1.6.6.2 Half-Pass TGs 49

1.6.6.3 N-Channel Half-Pass Transistor Charging Time Constant 49

1.6.6.4 Half-pass Transistor TG Discharge Time Constant 49

1.6.6.5 P-Channel Half-Pass Transistor Charging Time Constant 49

1.6.6.6 Inverter Propagation Delay Time Constants 50

1.6.6.7 High-to-Low and Low-to-High Transition Time 50

1.6.6.8 Inverter Propagation Delay Time 51

1.6.6.9 Series N-channel MOSFETs Discharge Delay Time 51

1.6.6.10 Series P-channel MOSFETs Charge Delay Time 51

1.6.7 Chip-Level Time Constants 52

1.6.7.1 Peripheral I/O Power Bus Time Constant 52

1.6.7.2 Core Chip Time Constant 53

1.6.7.3 Substrate Time Constants 53

1.6.7.4 Package Time Constants 54

1.6.8 ESD Time Constants 54

1.6.8.1 ESD Events 55

1.6.8.2 HBM Characteristic Time 55

1.6.8.3 mm Characteristic Time 56

1.6.8.4 CDM Characteristic Time 57

1.6.8.5 Charged Cable Model Characteristic Time 57

1.6.8.6 CDE Model 57

1.6.8.7 CCM Characteristic Time 58

1.6.8.8 TLP Model Characteristic Time 58

1.6.8.9 VF-TLP Model Characteristic Time 59

1.7 Capacitance, Resistance, and Inductance and ESD 59

1.7.1 The Role of Capacitance 59

1.7.2 The Role of Resistance 60

1.7.3 The Role of Inductance 61

1.8 Rules of Thumb and ESD 62

1.8.1 ESD Design: An "ESD Ohm's Law"-A Simple ESD Rule-of-Thumb Design Approach 62

1.9 ESD Scaling 63

1.10 Lumped versus Distributed Analysis and ESD 65

1.10.1 Current and Voltage Distributions 65

1.10.2 Lumped versus Distributed Systems 66

1.10.3 Distributed Systems-Ladder Network Analysis 67

1.10.4 RLC Distributed Systems 69

1.10.5 Resistor-Capacitor (RC) Distributed Systems 74

1.10.6 RG Distributed Systems 77

1.11 ESD Metrics: Chip-Level ESD Metrics and Figures of Merit 79

1.11.1 Chip Mean Pin Power-to-Failure 80

1.11.2 Chip Pin Standard Deviation Power-to-Failure 80

1.11.3 Chip Mean Pin Power-to-Failure to ESD Specification Margin 80

1.11.4 Worst-Case Pin Power-to-Failure to Specification ESD Margin 81

1.11.5 Total ESD Area to Total Chip Area Ratio 81

1.11.6 ESD Area to I/O Area Ratio 81

1.11.7 Circuit ESD Metrics 82

1.11.7.1 Circuit ESD Protection Level to ESD Loading Effect 82

1.11.7.2 Circuit Performance to ESD Loading Effect 82

1.11.7.3 ESD Area to Total Circuit Area Ratio 83

1.11.7.4 Circuit ESD Level to Specification Margin 83

1.11.7.5 Device ESD Metric 83

1.12 ESD Quality and Reliability Business Metrics 84

1.13 Twelve Steps to Building an ESD Strategy 85

1.14 Summary and Closing Comments 86

Problems 87

References 87

2 Design Synthesis 94

2.1 Synthesis and Architecture of a Semiconductor Chip for ESD Protection 94

2.2 Electrical and Spatial Connectivity 95

2.2.1 Electrical Connectivity 95

2.2.2 Thermal Connectivity 95

2.2.3 Spatial Connectivity 96

2.3 ESD, Latchup, and Noise 96

2.3.1 Noise 97

2.3.2 Latchup 98

2.4 Interface Circuits and ESD Elements 98

2.5 ESD Power Clamp Networks 101

2.5.1 Placement of ESD Power Clamps 104

2.6 ESD Rail-to-Rail Networks 105

2.6.1 Placement of ESD Rail-to-Rail Networks 107

2.6.2 Peripheral and Array I/O 107

2.7 Guard Rings 109

2.8 Pads, Floating Pads, and No-connect Pads 111

2.9 Structures under Bond Pads 112

2.10 Mixed Signal Architecture: CMOS 112

2.10.1 Digital and Analog CMOS Architecture 114

2.10.2 Digital and Analog Floor Plan: Placement of Analog Circuits 114

2.11 MS Architecture: Digital, Analog, and RF Architecture 116

2.12 Digital-to-Analog Interdomain Signal Line Failures 118

2.12.1 Digital-to-Analog Core Spatial Isolation 120

2.12.2 Digital-to-Analog Core Ground Coupling 120

2.12.3 Digital-to-Analog Core Resistive Ground Coupling 120

2.12.4 Digital-to-Analog Core Diode Ground Coupling 120

2.12.5 Domain-to-Domain Signal Line ESD Networks 122

2.12.6 Domain-to-Domain Third-Party Coupling Networks 122

2.12.7 Domain-to-Domain Cross-Domain ESD Power Clamp 123

2.13 Summary and Closing Comments 124

Problems 124

References 125

3 MOSFET ESD Design 129

3.1 Basic ESD Design Concepts 129

3.2 ESD MOSFET Design: Channel Length 136

3.2.1 Channel Length and Linewidth Control 136

3.2.2 ACLV Control 138

3.2.3 MOSFET ESD Design Practices 142

3.3 N-Channel MOSFET Design: Channel Width 143

3.4 ESD MOSFET Design: Contacts 144

3.4.1 Gate-to-Contact Spacing 144

3.4.1.1 Off-Axis Current Distribution 148

3.4.1.2 Self-Heating Equienergy Contours 148

3.4.2 Contact-to-Contact Space 149

3.4.3 ESD Design: End Contact 152

3.4.4 ESD MOSFET Design: Contacts to Isolation Edge 153

3.5 ESD MOSFET Design: Metal Distribution 153

3.5.1 MOSFET Metal Bus Design and Current Distribution 153

3.5.2 MOSFET Ladder Network Model 154

3.5.3 MOSFET Wiring: Parallel Current Distribution 158

3.5.4 MOSFET Wiring: Antiparallel Current Distribution 162

3.6 ESD MOSFET Design: Silicide Masking 165

3.6.1 ESD MOSFET Design: Silicide Mask Design 165

3.6.2 ESD MOSFET Design: Silicide Mask Design over Source and Drain 166

3.6.3 ESD MOSFET Design: Silicide Mask Design over Gate 167

3.7 ESD MOSFET Design: Series Cascode Configurations 170

3.7.1 MOSFET ESD Design: Series Cascode MOSFET 170

3.7.2 Integrated Cascoded MOSFETs 171

3.8 ESD MOSFET Design: Multifinger MOSFET Design-Integration of Coupling and Ballasting Techniques 174

3.8.1 Grounded-Gate Resistor-Ballasted MOSFET 174

3.8.2 Soft Substrate Grounded-Gate Resistor-Ballasted MOSFET 176

3.8.3 Gate-Coupled Domino Resistor-Ballasted MOSFET 177

3.8.4 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with MOSFET 179

3.8.5 MOSFET Source-Initiated Gate-Bootstrapped Resistor-Ballasted Multifinger MOSFET with Diode 180

3.9 ESD MOSFET Design: Enclosed Drain Design Practice 181

3.10 ESD MOSFET Interconnect Ballasting Design 182

3.11 ESD MOSFET...